ADC-Free Compute-in-Memory for Error-Resilient and Energy-Efficient AI Accelerators

Abstract

Analog compute-in-memory (CIM) has recently emerged as a novel paradigm for artificial intelligence compute, but the efficiency of CIM is heavily bottlenecked by the energy and area overhead of analog-to-digital (ADC). While replacing high-precision ADCs with 1-bit conversion significantly reduces peripheral overhead, binarization of crossbar-level partial sums introduces substantial information loss, leading to accuracy degradation. Therefore, aggressive partial sum binarization for high-precision (multi-bit) workloads remains a significant challenge for CIM. In this work, we address this challenge by proposing a synergistic framework combining ADC-free quantization with novel mapping schemes. We first established the insight that computations on the most/least significant bits (MSB/LSB) exhibit different sensitivities to ADC quantization errors. Exploiting this insight, we propose a novel mapping scheme to maximize system efficiency while maintaining near-lossless functional accuracy. First, we propose to use 1 bit/cell for MSB and 2-3 bits/cell for LSB, which is termed “unbalanced bit-slicing” (UBS). Second, we map the MSBs and LSBs to subarrays with different sizes (“array-split”). Simulation results on ResNet20/CIFAR-10 demonstrate up to $\mathbf{1 2} \times$ energy and $\mathbf{1 8 . 6} \times$ area efficiency improvement over the conventional CIM baseline with 6-bit ADCs. We further verified the error resilience of the proposed weight-mapping scheme based on the characteristics of fabricated ReRAM test chips. Our ADC-free framework demonstrates elimination of the ADC bottleneck and variability-resilient nearlossless inference accuracy on standard benchmarks.