Aug 2026· Midwest Symposium on Circuits and Systems· pp. 850-854· 0 citations· 17 references
Abstract
This paper presents the deployment of a speechbased Alzheimer’s disease classification CNN on the Xilinx Kria KV260 edge FPGA platform using hardware–software co-design. A lightweight 76,082-parameter network operating on log-Mel spectrograms is trained on a combined 160-sample dataset and quantized to INT8 using post-training quantization with the Vitis-AI toolchain. Audio preprocessing runs on the ARM Cortex-A53, while inference is offloaded to the DPUCZDX8G Deep Processing Unit. The FP32 baseline achieves 87.5% accuracy; post-training INT8 quantization yields 84.4% for both CPU and FPGA configurations, with INT8 FPGA and INT8 CPU producing identical predictions under strict preprocessing alignment. The deployed system achieves 0.876 ms inference latency and 1140+ FPS throughput, a $7.4 \times$ speedup over FP32 CPU execution at 157.7 FPS/W energy efficiency, compared to 26.2 FPS/W for CPU inference. These results confirm reliable FPGA acceleration for biomedical speech inference and highlight the critical role of preprocessing alignment and quantization consistency in edge deployment.
The deployment of deep learning models for Traffic Sign Recognition Systems (TSRS) in real-world Advanced Driver Assistance Systems (ADAS) is often constrained by the limited computational resources of embedded platforms. This paper presents a comprehensive hardware-software co-design solution for implementing a lightw...
Lam Duc Khai, Cong-Khoi-Duong Le, Hoang Dinh Bao Pham et al.· International Conference on...· 0 citations
CNN inference on edge hardware is constrained by memory bandwidth, redundant logic, and the area overhead of fully parallel multiply-accumulate (MAC) units. This paper presents a hardware-efficient CNN accelerator with an SRAM-based architecture optimised for classifying 28×28 grayscale images. Input images are ingeste...
Avinash Krishna Pk, R. S· International Conference Inn...· 0 citations
As the volume of data recorded by embedded edge sensors increases, particularly from neuromorphic devices producing discrete event streams, there is a need for hardware-aware neural architectures that enable efficient, low-latency and energy-conscious local processing. To address this research gap, we present an FPGA i...
K. Jeziorek, Piotr Wzorek, Krzysztof Błachut et al.· ACM Transactions on Reconfig...· 0 citations
The rapid development of programmable network devices and the widespread adoption of machine learning (ML) in networking have facilitated efficient research into intelligent data planes (IDPs). Offloading ML to programmable data planes (PDPs) enables quick analysis and responses to network traffic dynamics, and efficie...
Xiaoquan Zhang, Mai Zhang, L. Cui et al.· IEEE Transactions on Network...· 0 citations
Results show that weight scaling outperforms PBA, while layer-wise bias optimization increases the accuracy from 80.33% to 84.13% without modifying the datapath width.
L. Krupp, M. Gross, Michael Graichen et al.· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.
