Hardware Implementation of a Secure Pipelined RISC-V Core with Boolean Masking and Efficient Arithmetic Units on FPGA

Abstract

Edge devices are performing more sensitive work under loads, e.g., sensor fusion and embedded cryptography, with tight power constraints, and hence their processors are appealing targets. and is also requiring efficient arithmetic as well as sidechannel attacks. This is an improved 32-bit RISC-V soft core based on the RV32IM ISA and a classical five-stage pipeline with three important extensions: multi-hardware. multiply/divide unit, first-order Boolean masking built-in in critical datapaths, and a dynamic fine-grained power management scheme. Its processor is aimed at a Xilinx Zynq-7000 SoC (Zybo Z7) platform and given at the RTL level synthesis on low-cost FPGA devices. The Boolean masking scheme is employed to protect sensitive intermediate values within the arithmetic units and the ALU, thereby mitigating power-based side-channel leakage without revealing unmasked data inside the processor core. To compensate for the additional power overhead introduced by these security measures, an activity-aware clock-gating controller is integrated, which dynamically disables inactive logic blocks. This approach not only improves energy efficiency but also enhances the overall energy-delay product. The effectiveness of the proposed design is validated through a comparative analysis of masked and unmasked configurations, considering key metrics such as timing performance, resource utilization, and power consumption. The results indicate that substantial resistance to side-channel attacks can be achieved while maintaining power consumption within the range of approximately 0.09 W to 0.17 W, without compromising the practical performance required for edge-class applications.