A High-Linearity Hybrid-Domain SRAM-CIM Macro With Wide-Margin Voltage-to-Time Interface and Process-Adaptive TDC

Abstract

SRAM-based computing-in-memory (SRAM-CIM) alleviates the memory-wall bottleneck of the von Neumann architecture, enabling energy-efficient AI edge computing. Current-domain CIM schemes suffer from degraded linearity at low supply voltages, whereas time-domain CIM schemes are highly sensitive to process, voltage, and temperature (PVT) variations. This paper presents a hybrid-domain SRAM-CIM macro featuring enhanced linearity and process-adaptive quantization. Specifically, a current mirror discharge and inverting Schmitt trigger (CMD-IS) module converts bit-line voltage-signals into time-signals, alleviating discharge nonlinearity while ensuring a uniform slew rate. Additionally, guided by statistical analysis of the column-wise multiply-and-accumulate (MAC) value probability distribution, a resolution-tunable stepwise-encoded time-to-digital converter (RTSE TDC) reduces quantization overhead, while a process corner detection and delay regulation (PDDR) module adaptively calibrates TDC quantization steps to compensate for process corner variations. Implemented in 28 nm CMOS technology, the macro achieves peak energy efficiencies of 29.88 TOPS/W and 36.88 TOPS/W in signed and unsigned CIM modes, respectively, with area efficiencies of 6.00 TOPS/mm2 and 5.88 TOPS/mm2. For the ResNet-20@CIFAR-10 and ResNet-20@CIFAR-100 datasets, the macro achieves inference accuracies of 91.33% and 67.43%.