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WestLake: Accelerating Fully Homomorphic Encryption With Less On-Chip Memory

Oct 2026 · IEEE Transactions on Very Large Scale Integration (vlsi) Systems · Vol 34, pp. 3323-3336 · 0 citations · 52 references

Abstract

Fully homomorphic encryption (FHE) enables computation on encrypted data without decryption. This makes FHE a valuable privacy-preserving technique applicable in fields such as private machine learning (ML). FHE achieved unlimited homomorphic operations on ciphertext by periodic bootstrapping, which is highly time-consuming. To accelerate FHE, various hardware accelerators have been proposed. However, most FHE accelerators rely on massive on-chip memory to mitigate the off-chip memory bandwidth bottleneck, resulting in a large chip area. We propose WestLake, a memory-efficient accelerator for FHE. To reduce on-chip memory size, we make efforts on algorithmic optimizations, data scheduling, and architectural design. First, we propose several algorithmic optimizations that reduce both on-chip memory size and off-chip memory access. Second, we devise a memory-efficient dataflow for bootstrapping, which leverages the overlapping between computing and data transfer, maximizes data reuse by reordering operations, and balances on-chip memory size and off-chip bandwidth requirements. Finally, we propose WestLake architecture, which features tailored function units (FUs) for primary FHE operations and integrates our algorithmic optimizations and memory-efficient dataflow. WestLake reduces resource usage by enabling a single unit to handle two primary FHE operations (base conversion (BConv) and element-wise operation). In contrast to the state-of-the-art Cheon–Kim–Kim–Song (CKKS) accelerator SHARP, which used 198 MB on-chip memory, WestLake only utilizes 80 MB on-chip memory. Compared to SHARP, WestLake achieves a speedup of <inline-formula> <tex-math notation="LaTeX">$1.7\times $ </tex-math></inline-formula> in geometric mean with <inline-formula> <tex-math notation="LaTeX">$2.1\times $ </tex-math></inline-formula> smaller chip area and <inline-formula> <tex-math notation="LaTeX">$1.6\times $ </tex-math></inline-formula> less power consumption.

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