HyPA: A Low-Latency Hybrid Pipeline Asynchronous Router for Network-on-Chip Architectures in GALS-Based SoCs

Abstract

As system-on-chip (SoC) designs continue to scale toward highly heterogeneous multicore architectures, the limitations of global clocking make communication increasingly challenging with lower technology nodes. Asynchronous network-on-chip (NoC) architectures offer an attractive solution for enabling scalable communication in globally asynchronous locally synchronous (GALS) systems. However, the practical adoption of asynchronous routers remains limited due to the design complexity of asynchronous circuits and their limited compatibility with conventional electronic design automation (EDA) tool flows. This article presents HyPA, a hybrid pipeline asynchronous router architecture for NoC communication in GALS-based SoCs. The proposed HyPA router is built on a high-throughput domino-logic pipeline template with a one-hot hybrid data encoding scheme, which facilitates a simple, scalable router architecture while maintaining compatibility with the conventional EDA flow. The HyPA router is implemented using the conventional EDA design flow targeting 65-nm United Microelectronics Corporation (UMC) technology and evaluated through postlayout back-annotated timing and power analysis. The HyPA router, when benchmarked against synchronous routers, showed 62% lower power consumption and an average 85% reduction in energy-per-flit under the same operational conditions. The router achieves a minimum forward latency of 0.8 ns and a throughput of 1.65 GFlits/port/s. The presented HyPA router shows better performance, despite a slight area overhead resulting from its asymmetric layout, when evaluated using a metric-based comparison against recently reported designs. These results illustrate the feasibility of implementing high-performance NoC routers in industrial SoC designs without specialized toolchains.