GTC: Architecture exploration for generation-in-time computing paradigm

Abstract

We propose Generation-in-Time Computing (GTC), a software-hardware co-design paradigm in which a centralized, large language model-based generation system translates real-time physical context and target hardware constraints into task-specific executable instruction streams. To realize this paradigm, we present Arch-X, a computation-centric edge architecture that exploits these specialized streams by eliminating or simplifying complex microarchitectural structures commonly used in high-performance processors. We evaluate GTC on three workloads: LLM-guided A* path planning, breadth-first search (BFS), and TinyEKF sensor fusion. For LLM-guided A*, GTC reduces the number of dynamic instructions by 68.8% and branch instructions by 81.9% relative to a predefined-computing baseline. Across all three workloads, GTC improves performance on both in-order and out-of-order processors. An Field Programmable Gate Array (FPGA) implementation further shows that Arch-X reduces lookup-table (LUT) and block-RAM (BRAM) usage by 71.1% and 86.2%, respectively, relative to a dual-issue out-of-order reference core, while retaining the arithmetic datapath required by the evaluated workloads. Together, these results provide preliminary evidence that resolving context-dependent control through centralized generation can reduce software overhead and enable simpler edge hardware for efficient, adaptive computation.