Spiking Neural Network Chips for Low-Power Real-Time Edge Intelligence

Abstract

Edge devices require short response time and low active and idle power, yet conventional neural-network hardware repeatedly moves weights and activations between memory and processing units. Spiking neural network (SNN) chips address this problem with event-driven communication, persistent neuron state, and local synaptic storage. This review first explains the signal path of an SNN chip through four connected modules: spike encoding, neuron computation, synaptic learning, and output decoding. It then compares three implementation routes: digital many-core platforms, mixed-signal or sensor-integrated platforms, and memristive in-memory hardware. Representative systems include TrueNorth, Loihi, Tianjic, Darwin3, ODIN, DYNAP-SE, and Speck. The comparison shows that no single metric is enough. Large digital chips provide scale and programmability but still incur memory and routing costs; mixed-signal and sensor-integrated designs reduce unnecessary activity but require attention to device mismatch and input-event rate; memristive arrays reduce weight movement but remain sensitive to variation and peripheral overhead. Meaningful evaluation therefore requires accuracy, timestep count, event activity, latency, active and idle power, and a clear measurement boundary. These criteria help identify when SNN hardware offers a practical advantage for low-power real-time edge intelligence.