Aug 2026· International Journal of Wavelets, Multiresolution and Information Processing· 0 citations
TL;DR
A comparative analysis of dynamic stochastic computing using a convolutional neural network for MNIST digit classification indicates that dynamic stochastic computing can serve as an efficient alternative for the design and implementation of neural-network accelerators.
Abstract
Deep neural networks achieve state-of-the-art performance in many vision tasks but require substantial computational resources and energy, making their deployment on edge devices and embedded platforms challenging. Several approaches have been proposed to address this challenge, including fixed-point arithmetic, stochastic computing (SC), and dynamic stochastic computing (DSC). This work presents a comparative analysis of these approaches using a convolutional neural network (CNN) for MNIST digit classification. The study compares floating-point inference, fixed-point quantized inference, stochastic computing using bitstream representations, and dynamic stochastic computing using accumulation with stochastic integrators. Performance is evaluated in terms of classification accuracy, cross-entropy loss, runtime latency, and throughput across different bit-widths and stochastic bitstream lengths. The results demonstrate the trade-offs among numerical precision, computational latency, and inference accuracy. Fixed-point implementations provide high throughput with minimal accuracy degradation at moderate bit-widths, whereas stochastic computing reduces arithmetic complexity but requires longer bitstreams to achieve comparable accuracy. Dynamic stochastic computing exhibits improved convergence characteristics compared with conventional stochastic computing. These results indicate that dynamic stochastic computing can serve as an efficient alternative for the design and implementation of neural-network accelerators.
Low-level hardware acceleration strategies to deconstruct the mapping from algorithm logic to silicon substrates are reviewed to provide strong guidelines for the hardware-software co-design of emerging ultra-low power edge Artificial Intelligence (AI) chips.
Linenxu Zhang· MATEC Web of Conferences· 0 citations
For moderate levels of approximation, the energy saving was significant and larger for more aggressive approximation; for aggressive approximation with less precision, the drop in accuracy was steep, and the paper ends with a discussion on accuracy vs. energy.
M. Zafar· ComputeX - Journal of Emergi...· 0 citations
Findings confirm that combining complementary compression strategies yields substantially better performance-efficiency trade-offs than any single technique applied in isolation.
Upma Sharma Archana· International Journal of Res...· 0 citations
The authors introduce the Edge Suitability Score (ESS), a composite metric that combines normalized accuracy, model size, and inference speed into a single value, weighted at 0.40, 0.35, and 0.25 to reflect their relative importance for microcontroller deployment.
Results confirm that learning-augmented arithmetic units provide an effective and scalable solution for next-generation nonlinear floating-point computation.
K. Pande, P. Karule· International journal of com...· 0 citations
APEX is presented, a dual-sparsity SNN inference accelerator that integrates the PASC-IF neuron into the LoAS hardware framework, and guarantees mathematical equivalence between the converted SNN and the source ANN, thereby achieving ANN-equivalent accuracy at significantly reduced timesteps.
D. Venkatesh, S. Radhakrishnan, Rajshekhar Rakshit et al.· 0 citations
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