Aug 2026· International Journal of Wavelets, Multiresolution and Information Processing· 0 citations
TL;DR
A comparative analysis of dynamic stochastic computing using a convolutional neural network for MNIST digit classification indicates that dynamic stochastic computing can serve as an efficient alternative for the design and implementation of neural-network accelerators.
Abstract
Deep neural networks achieve state-of-the-art performance in many vision tasks but require substantial computational resources and energy, making their deployment on edge devices and embedded platforms challenging. Several approaches have been proposed to address this challenge, including fixed-point arithmetic, stochastic computing (SC), and dynamic stochastic computing (DSC). This work presents a comparative analysis of these approaches using a convolutional neural network (CNN) for MNIST digit classification. The study compares floating-point inference, fixed-point quantized inference, stochastic computing using bitstream representations, and dynamic stochastic computing using accumulation with stochastic integrators. Performance is evaluated in terms of classification accuracy, cross-entropy loss, runtime latency, and throughput across different bit-widths and stochastic bitstream lengths. The results demonstrate the trade-offs among numerical precision, computational latency, and inference accuracy. Fixed-point implementations provide high throughput with minimal accuracy degradation at moderate bit-widths, whereas stochastic computing reduces arithmetic complexity but requires longer bitstreams to achieve comparable accuracy. Dynamic stochastic computing exhibits improved convergence characteristics compared with conventional stochastic computing. These results indicate that dynamic stochastic computing can serve as an efficient alternative for the design and implementation of neural-network accelerators.
Edge computing and artificial intelligence have made the efficient deployment of machine vision algorithms on low-power hardware a critical challenge for integrated circuit design. Given data-intensive image pixels and deep neural network tensors, traditional von Neumann architectures inevitably encounter severe memory and power wall bottlenecks. This paper reviews low-level hardware acceleration strategies to deconstruct the mapping from algorithm logic to silicon substrates. Through systematic analysis, physical dimensionality reduction and operator substitution effectively reduce computational complexity and enhance energy efficiency. For visual preprocessing, line-buffer topologies and multiplier-less shift-and-add designs optimize bandwidth and eliminate DSP dependencies for certain edge detectors. In edge-based inference, 8-bit fixed-point quantization slashes system bus bandwidth demands by over 75% while restricting accuracy degradation to under 0.5%. Concurrently, Winograd fast convolution translates spatial convolutions into transform-domain mappings, substantially reducing core multiplier utilization and driving significant system throughput. Additionally, advanced dataflow scheduling circumvents power-hungry off-chip memory accesses by maximizing on-chip data reuse and resolving dynamic energy crises. Ultimately, these findings provide strong guidelines for the hardware-software co-design of emerging ultra-low power edge Artificial Intelligence (AI) chips.
Linenxu Zhang· MATEC Web of Conferences· 0 citations
With the increasing computational and energy requirement for deep neural network (DNN) inference, energy efficiency is becoming a first-order system design constraint for deploying an AI system on power and battery constrained platforms. One attractive design paradigm that has recently emerged is approximate computing, which leverages the existing error resilience of DNNs to sacrifice a fraction of accuracy for a much bigger reduction of energy consumption. This research employed an experiment-based computer-systems evaluation approach to assess the effectiveness of approximate computing techniques in achieving energy efficiency for AI inference without compromising computational accuracy. Using selected deep learning models, a representative set of AI inference workloads, such as image classification workloads and workloads performing prediction using neural networks, were implemented, and various approximation techniques were introduced at different computational levels: reduced numerical precision, approximate arithmetic operations, quantization, and selective computation, with a conventional exact-computing implementation acting as the baseline against which the performance of the various approximations was compared. To demonstrate the reporting procedure this experimental design suggests, illustrative, not hardware-measured results are reported and interpreted as what these metrics would look like if hardware-energy measurements were made. The results presented in the illustrative pattern matched well the results which are abundantly reported in the approximate-computing literature: for moderate levels of approximation, the energy saving was significant and larger for more aggressive approximation; for aggressive approximation with less precision, the drop in accuracy was steep. The paper ends with a discussion on accuracy vs. energy, how this trade-off would affect the adoption of AI to constrained resources, and future directions for research validated by hardware.
M. Zafar· ComputeX - Journal of Emergi...· 0 citations
Findings confirm that combining complementary compression strategies yields substantially better performance-efficiency trade-offs than any single technique applied in isolation.
Upma Sharma Archana· International Journal of Res...· 0 citations
The authors introduce the Edge Suitability Score (ESS), a composite metric that combines normalized accuracy, model size, and inference speed into a single value, weighted at 0.40, 0.35, and 0.25 to reflect their relative importance for microcontroller deployment.
Nonlinear computations plays a critical role in modern applications such as deep learning, digital signal processing, cryptography, and scientific modelling, yet conventional IEEE-754 floating-point units struggle to meet the conflicting demands of high precision, low latency, and energy efficiency. Static data paths, fixed-precision formats, and polynomial-based approximations limit their adaptability and numerical robustness, particularly for transcendental and nonlinear operations. In this work, a deep learning–augmented floating-point arithmetic architecture is proposed to address these limitations. The architecture integrates five complementary learning-enabled modules: adaptive latency optimization using a reinforcement learning–based micro-scheduler, context-aware runtime error estimation and compensation, dynamic bit-width control through precision-aware deep bandwidth scaling, gradient-informed neural approximation of nonlinear functions, and domain-aware transfer learning for rapid arithmetic unit adaptation across applications. The proposed design is evaluated using FPGA-based hardware–software co-simulation on representative workloads from neural networks, signal processing, and cryptographic domains. Experimental results show substantial improvements, including latency reductions of up to 63%, numerical error reduction exceeding 70% with accuracy within ±0.5 ULP, power savings of up to 59%, and area reductions beyond 40%. Furthermore, application-level validation demonstrates negligible degradation in inference accuracy and significant reductions in retraining overhead across domains. These results confirm that learning-augmented arithmetic units provide an effective and scalable solution for next-generation nonlinear floating-point computation.
K. Pande, P. Karule· International journal of com...· 0 citations
Spiking Neural Networks (SNNs) have emerged as an energy-efficient alternative to Artificial Neural Networks (ANNs), leveraging sparse accumulate operations in the place of power-hungry multiply-and-accumulate operations. ANN-SNN conversion is a widely adopted approach to realize deep SNNs with accuracy comparable to that of ANNs. The Quantization-Clip-Floor-Shift (QCFS) activation minimizes conversion error, yet requires a large number of inference timesteps to match the source ANN accuracy on real-world vision datasets. PASCAL addresses this by proposing the Precise ANN-SNN Conversion Integrate-and-Fire (PASC-IF) neuron, which guarantees mathematical equivalence between the converted SNN and the source ANN, thereby achieving ANN-equivalent accuracy at significantly reduced timesteps. Despite this algorithmic advancement, the hardware implications of deploying the PASC-IF neuron remain unexplored. In this work, we present APEX, a dual-sparsity SNN inference accelerator that integrates the PASC-IF neuron into the LoAS hardware framework. The three-stage PASC-IF datapath is realized as a fully combinational circuit with no additional latency cost. APEX exploits dual sparsity in both input spikes and weights through a fully temporal-parallel dataflow, enabling efficient sparse computation and reduced memory traffic. Across all evaluated models, the PASC-IF neuron on average achieves up to 3% higher accuracy than the standard IF neuron, with a power overhead of only 1.3%-5.4%, an area overhead of 2.1%-2.7%, and 40% energy reduction for best accuracy configurations.