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AI and Computational Simulation Platform for Advancing Silicon-Compatible Materials

Jul 2026 · ECS Meeting Abstracts · 0 citations

TL;DR

A platform that integrates artificial intelligence (AI) with advanced computational simulations beyond DFT, designed to accelerate the design and optimization of materials for high-performance applications in electronics, photonics, and energy technologies is presented.

Abstract

The development of silicon-compatible materials for next-generation CMOS and post-CMOS technologies requires more precise and efficient methods for material discovery and optimization. Traditional computational approaches like density functional theory (DFT) often fail to capture the full complexity of materials at the atomic and electronic levels. To overcome these limitations, I will present a platform that integrates artificial intelligence (AI) with advanced computational simulations beyond DFT, designed to accelerate the design and optimization of materials for high-performance applications in electronics, photonics, and energy technologies. This platform leverages both advanced computational techniques and machine learning to offer more accurate, scalable models for predicting the properties of novel materials. By going beyond traditional DFT, we can better capture complex phenomena such as excited-state properties and material behavior under different environmental conditions, which are critical factors for developing advanced materials like high-k dielectrics, wide-bandgap semiconductors (e.g., SiC, GaN), and ferroelectrics for neuromorphic computing. The platform enables high-throughput simulations, allowing us to explore a broad material space and predict how materials will perform under various physical conditions. This capability is key for optimizing materials across a range of applications, from low-power electronics to advanced photonic and energy systems. I will also focus on how this approach is applied to materials crucial for the advancement of future silicon-compatible technologies, such as those used in non-volatile memory, power electronics, and integrated photonics. Moreover, the platform facilitates the discovery of new materials with tailored properties, which are essential for applications like heterogeneous integration (HI), 2.5D/3D chip stacking, and optical interconnects, pushing the boundaries of high-bandwidth, high-performance systems. By combining AI with beyond-DFT computational methods, this platform provides a powerful, scalable approach to accelerate the discovery, optimization, and integration of materials for next-generation semiconductor and photonic systems. It offers a solution to overcoming material-related challenges, helping to drive the evolution of next-generation electronics and photonics.

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