From simulation results, it is shown that piSlip with virtual cut-through offers latency characteristics significantly better than unmodified iSlip with similar packet port interfaces and Simulation further shows that piSlip and iSlip have similar maximum and average buffering requirements.
Abstract
This paper examines input/output buffered crossbar switches under combined packet and cell data. Our switch architecture uses input buffering with Virtual Output Queues to avoid Head of Line Blocking. The switch fabric is a crossbar with no speedup. We use a modified iSlip [McKeown] crossbar scheduler geared towards packet data, called piSlip. Cell ports are largely unmodified from standard iSlip behavior. For packet output ports, we introduce changes to the grant pointer which minimizes output latency caused by packet reassembly. Our model uses several output states, including packet cut-through. From simulation results, we show that piSlip with virtual cut-through offers latency characteristics significantly better than unmodified iSlip with similar packet port interfaces. Simulation further shows that piSlip and iSlip have similar maximum and average buffering requirements.
A parallel packet switch (PPS) is a switch in which the memories run slower than the line rate.
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packet switches. It is already known that with a speedup of, a PPS can theoretically mimic a
FCFS output-queued (OQ) switch. Howev...
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