Design and Simulation of CMOS Operational Amplifier

Abstract

This paper presents the design, systematic sizing, and comprehensive simulation of a two-stage Miller-compensated complementary metal-oxide-semiconductor (CMOS) operational amplifier (op-amp) in a 180 nm technology with a 1.8 V supply. A square-law-driven design methodology was employed to translate circuit-level specifications into device geometries, compensation elements, and bias conditions prior to simulation. The amplifier achieves a DC gain of 71.9 dB, a unity-gain bandwidth of 10 MHz with a 60° phase margin, a slew rate of 10 V/µs, a common-mode rejection ratio of 74 dB, and a power dissipation of 0.378 mW while driving a 10 pF load. Process–voltage–temperature (PVT) corner analysis and Monte Carlo mismatch simulations confirm that the design retains stable frequency compensation across all corners, with the phase margin bounded between 54° and 66°. The simulated performance agrees with hand-calculated predictions within 5%, validating the adopted synthesis flow. The results indicate that the classical two-stage topology, when properly compensated with a nulling-resistor-controlled Miller capacitor, remains a competitive solution for moderate-bandwidth, low-power analog interfaces