FPGA-Based Softmax Approximation: Analytical Cost–Error Modeling and Pareto Optimization

Abstract

The softmax function is a significant bottleneck in FPGA-based Transformer inference. This paper presents a comprehensive analytical framework for the design and optimization of base-2 softmax on FPGAs through systematic design-space exploration. We derive a high-accuracy LUT6 cost model that captures all major pipeline components, along with a closed-form error model for the exponential approximation, validated against Monte Carlo simulation with deviations below 10% for MSE and within 2% for MAE. By jointly leveraging these models, we exhaustively explore the design space and identify Pareto-optimal configurations that minimize LUT6 usage for a given relative error target. We further propose a negligible-cost fixed-maximum-subtraction scheme that eliminates the sorting network required by prior work, and introduce a bipartite exponential architecture that removes the intrinsic approximation floor of piecewise-linear methods. Synthesis and implementation on a Xilinx UltraScale+ FPGA confirm the effectiveness of the proposed approach. For a single-lane configuration, the optimized core requires only 201 LUT6s to achieve a relative MSE below $10^{-10}$ , corresponding to an approximately 49% reduction in resource utilization compared to the closest prior work at comparable accuracy.