Modular End-to-End Pipeline for Formal Property Verification using Large Language Models

Benchmarking LLMs for Verilog Design Flows

A reproducible benchmarking platform that evaluates open-source LLMs on Verilog RTL generation across 50 curated tasks consisting of combinational, sequential, finite state machine (FSM), and mixed designs, enabling reproducible evaluation of generative AI for hardware design workflows.

QiMeng-VPID: Verification-Grounded Port-Level Iterative Decomposition for Complex Verilog Generation

This work proposes VPID, a multi-agent framework for generating complex Verilog that achieves monotonic functional improvement and introduces an experience-guided refinement strategy that distills historical waveform mismatches into constraints, guiding the targeted debugging for the unverified ports.

VClare: Resolving Imperfect Specifications in LLM-Based Verilog Generation

The first systematic study of imperfect specifications is presented and an automated framework to repair them to enhance the quality of resulting Verilog design is proposed, demonstrating the capabilities of specification repair by {VClare} as well as further potential of LLMs in front-end hardware design.

Formalization of a Realistic Verification-Condition Generator for an Intermediate Verification Language

Polymorphic coverage types ∗

When Fuzzing Meets Understanding: LLM-Driven Semantic Test Generation for RTL Verification

ChipFuzzer is proposed, a hardware fuzzing framework that leverages the semantic reasoning capabilities of large language models (LLMs) to improve fuzzing effectiveness and improves average condition coverage and bug detection rate over the strongest baseline.