Many irregular neural workloads induce skewed many-to-one reductions with repeated neighborhoods and nonlocal communication. Conventional NoC mappers optimize placement and routes for a fixed communication graph, even though associative reductions expose legal opportunities to eliminate traffic before routing. We present MeshReduce-U, a compiler-guided communication-reduction and routing framework for mesh-NoC-based spatial accelerators. MeshReduce-U coalesces colocated sources, forms local aggregation islands, blocks channels with compatible fan-in structure, selects capacity-feasible sinks, and routes the remaining fixed-width carriers using fused usage-aware costs. A deterministic route-replay model reports schedule-derived communication latency, total link usage (TLU), and fused link usage (FusedTLU) separately. Across a 20-workload lowerable neural-network zoo, MeshReduce-U reduces mean latency, TLU, and FusedTLU by 40.3%, 56.0%, and 48.7%, respectively, relative to an ABC-style source-aggregation baseline, improving all three metrics on every workload. Across 40 synthetic irregular reductions, it reduces mean latency and TLU by 12.3% and 19.7%. A new 30-instance pass-by-pass study further shows that the structural rewrites reduce the global carrier count by 60.9% and replay latency by 63.0%. These results show that rewriting reducible neural communication before routing can be more effective than searching harder over an unreduced traffic graph.
Task placement strongly affects the on-chip communication overhead of Network-on-Chip (NoC)-based deep-neural network (DNN) accelerators. This work addresses task-to-core mapping on two-dimensional (2D) Concentrated Mesh (CMesh) NoCs with the explicit objective of minimizing communication cost, defined as the traffic-w...
Alperen Cakin, Selma Dilek, S. Tosun et al.· International Symposium on N...· 0 citations
VarioPath, an efficient AlltoAllv scheduling framework for PCIe GPU systems that combines an offline topology-aware analyzer with an online demand-aware scheduler, and shows average AlltoAllv speedups of 5.88x over FAST and 1.72x over DeepEP.
Yao Fei, Jin Fang, Si-Ze Zheng et al.· 0 citations
The core of LEO lies in introducing hierarchical caching to construct a hybrid-grained software pipeline, enabling efficient computation-communication overlap both within and across GPU kernels.
Jia-Qi Si, De-Zun Dong· ACM Transactions on Architec...· 0 citations
Mixture-of-experts (MoE) models expand capacity via sparse activation, but inference across GPUs introduces tensor-parallel (TP) collectives and expert-parallel (EP) dispatch and combine operations. Completion time depends not just on communication volume but on how logical groups map onto intra-server interconnects, G...
Processing-in-Memory (PIM) on monolithic 3D (M3D) DRAM is a promising answer to the memory wall for data-intensive dynamic programming (DP), yet extracting its performance today demands hand-written kernels: the programmer must pick a tile size, place data across non-uniform-latency memory tiers, partition work between...
Mahbod Afarin, Tsung-Han Lu, T. Rosing· 0 citations
A multi-cluster architecture that replaces inter-cluster communication with localized data replication within ScratchPad Memories (SPMs) is introduced, creating a critical architectural trade-off between the data replication overhead required by overlapping-footprint kernels and the routing delays of larger clusters.
Chanon Khongprasongsiri, P. Tanguy, Kevin J. M. Martin et al.· IEEE International Conferenc...· 0 citations
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