Characterizing the simulation of system behaviors for requirement verification using SysML

Abstract

The development of executable SysML models is typically completed without understanding which SysML diagrams, elements, and ancillary aspects such as verification languages, etc. are needed to simulate system behaviors. This produces static models that need to be reworked to support requirement verification or other systems engineering tasking. Characterizing system behaviors in terms of executable methods organizes potential SysML simulation categories and relates the executable models to systems engineering tasking which will increase the complexity of modeling efforts and realize the simulation capabilities for verifying requirements in SysML. The methods that will be developed include the use of Association Blocks to complete informational exchange without behavioral elements and diagrams, Signals and Activities for one-way informational transfer, as well as specialized methods for nested points of interface and self-reinforcing or multi-layered structures, Messages and Interactions for varied informational exchange, State Machines for state-based behaviors, and combinations of methods for simple, medium, and complex system dynamics. Examples of the applications of these methods include a cable system verifying electrical current, a computing system sending data from a processor to a reader, as well as variations for nested ports and multi-layered readers, a computing system sending and modifying data to containers via a state’s entering, ongoing, and exiting activities, a computing system sending and modifying data to containers by transitioning between states, and a user withdrawing money from an ATM. Each method demonstrates verification of requirements with differing levels of modeling complexity.