Implementation and Evaluation of two 32-Point Butterfly FFT Accelerators in a RISC-V Core

Abstract

This project integrates two 32-point Fast FourierTransform (FFT) accelerators into the RS5 RISC-V processor, afour-stage pipeline architecture supporting custom instructions.We evaluate two FFT accelerator designs (one with parallelinput/output and another with serial input/output), comparingtheir performance against a software-based FFT implementationrunning directly on the RISC-V core. The accelerator operatesindependently of the processor pipeline, interfacing with adedicated register bank and is triggered via a custom instruction.This instruction facilitates communication between the core, theregister bank, and the FFT module. The study encompasseslogical synthesis, physical synthesis, and behavioral analysis.The execution efficiency achieves a speedup of 2000× from thestandard processor with an acceptable increase of area and powerconsumption.