Low Power Hybrid Approximate Adder using BSPAA for Error Tolerant Applications

Abstract

Approximate computing is a promising way to improve energy efficiency and speed in applications where precise computation may not be necessary, like applications involving image processing. Within the domain, arithmetic circuits, especially adders, significantly influence the overall power usage and timing constraints. This work introduces a hybrid, compact, high-speed 32-bit adder using the Branch Skip Pattern-Aware Adder (BSPAA) framework, which is combined with efficient, inaccurate logic. The architecture of this adder is divided into two parts: a 10-bit part at the bottom where the inaccuracy is purposely increased to greatly lower its power needs, and a 22-bit part at the top that uses BSPAA to keep the calculations accurate and precise. BSPAA uses dynamic pattern recognition and branch skipping to check if operand bits are compatible. This lets the carry propagation happen only when it is essential. The implementation uses FPGA-optimized parts like LUT6_2, CARRY4, and MUXF7 to make synthesis more efficient and speed up the formation of carry chains. The experiment setup outcomes reveal the circuit occupies 19 LUTs consumes 0.103 W of power with 45.21% power saving. Despite the reduced precision in the lower section of the 10-bit inaccurate logic part, the error metrics remain favorable, with mean absolute error (MAE) near 115 and root mean square error (RMSE) around 158, and this solution offers a compelling balance among computational precision, area, and energy efficiency, making it highly suitable for systems that can tolerate limited inaccuracies.