Finfet-Based Low Power Sram Cell Design: A Comprehensive Review

Abstract

Static Random Access Memory (SRAM) remains the dominant on-chip memory technology, occupying over 50% of chip area in modern microprocessors and serving as the backbone of cache hierarchies, register files, and AI accelerators (Evolution of SRAM Architectures, 2026). As CMOS technology scaling approaches fundamental physical limits below 10 nm, conventional planar SRAM cells face critical challenges including excessive leakage power, degraded static noise margin (SNM), and heightened process variability sensitivity. FinFET technology has emerged as the dominant solution, offering superior electrostatic control through multi-gate architecture and demonstrated leakage reduction up to 40% with 10–20% SNM improvement compared to planar CMOS (Evolution of SRAM Architectures, 2026). This review provides a comprehensive examination of FinFET-based low power SRAM cell design methodologies, synthesizing findings from literature spanning 2018–2026. The review systematically analyzes architectural alternatives including conventional 6T configurations, 7T and 8T cells with decoupled read ports, 9T dual-port structures, and 10T variants optimized for stability and power. Read/write assist techniques including word-line under-drive (WLUD), transient voltage collapse (TVC), negative bit-line (NBL), and combined read-write assist strategies are comparatively evaluated. Emerging optimization approaches including metaheuristic algorithms and machine learning-informed design methodologies are examined. Key findings reveal that FinFET-based SRAM cells achieve substantial improvements across all performance metrics, with power dissipation as low as 0.985 μW, propagation delay of 0.97 ns, and PDP of 2.01 × 10⁻¹⁵ W-s demonstrated at advanced technology nodes (Improving FinFET Device Parameters, 2025). The review identifies critical trade-offs between stability, power, and area, providing guidance for technology selection based on application requirements.