Integration of Memristor Technology with CMOS: An AI-Based Hybrid Architecture for Neuromorphic Computing Applications

Abstract

Memristor-based neuromorphic computing is a promising approach for efficient AI processing. However, device variation and analog imperfections can affect computational reliability. This study proposes a hybrid architecture that combines an AI model with a conventional Complementary Metal-Oxide-Semiconductor (CMOS) fallback path to improve execution reliability. A lightweight AI model developed to classify four types of arithmetic and logical operations. The model trained and evaluated using a test set of 1,800 samples. The network architecture and required Multiply-Accumulate (MAC) operations were analysed to characterize its computational cost. A confidence-based mechanism then used to identify low-confidence decisions and route them to the CMOS fallback path. Energy and latency were analysed using published hardware references as analytical projections rather than direct hardware measurements. The AI model achieved 99.28% accuracy. The AI path processed 94.83% of the test samples, while 5.17% routed to the CMOS path. The hybrid system achieved 99.94% accuracy and corrected 12 of the 13 errors produced by the AI-only model. The results indicate that a CMOS fallback path can improve system reliability while limiting the use of conventional execution. Future work should implement the proposed architecture on physical hardware and directly measure its energy and latency. The effects of memristor variation and noise should also be investigated. Keywords: memristor, CMOS, computing-in-memory, neuromorphic computing, neural network, hybrid architecture, hardware-aware analysis