A Cyclic Vernier Time-to-Digital Converter With Tunable Time Amplification for Endpoint Clock-to-Data Interval Measurement in FPGAs
Abstract
Quantitative reconstruction of endpoint-local clock-to-data intervals during operation can complement static timing analysis (STA) when local process, voltage, and temperature (PVT) variation, supply disturbances, and aging shift setup margin. Existing in situ monitors are commonly either error-triggered, which require violation detection and recovery, or replica-based, which rely on path matching rather than direct endpoint observation. This article presents a cyclic vernier time-to-digital converter (TDC) measurement core that acts as a digital instrument for calibrated reconstruction of the clock-to-data interval at monitored endpoints in field-programmable gate arrays (FPGAs). Feedback recirculation accumulates a programmable per-cycle delay difference, providing tunable time amplification without proportionally extending the delay line. Implemented on an AMD/Xilinx Zynq UltraScale + MPSoC XCZU7EV FPGA, the single-channel prototype characterized the proposed measurement core over an input range of -15 to 967 ps. At the nominal programmable clock-path delay setting <inline-formula> <tex-math notation="LaTeX">$t_{\mathrm {CLK}}$ </tex-math></inline-formula> <inline-formula> <tex-math notation="LaTeX">$= {\mathrm {105~ps}}$ </tex-math></inline-formula>, it achieved a <inline-formula> <tex-math notation="LaTeX">$205.0\times $ </tex-math></inline-formula> time-amplification gain, a mean single-shot input-domain rms uncertainty of 11.59 ps (<inline-formula> <tex-math notation="LaTeX">$1\sigma $ </tex-math></inline-formula>), and maximum absolute integral nonlinearity (INL)/differential nonlinearity (DNL) in the input domain of 15.81/27.23 ps, using 339 lookup tables (LUTs) and about 5 mW core logic power. Across the full programmable sweep, the time-amplification gain was adjustable from <inline-formula> <tex-math notation="LaTeX">$181.8\times $ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$1067.5\times $ </tex-math></inline-formula>. These results show that the proposed architecture provides compact interval readout at monitored endpoints with characterized uncertainty, without error triggering or replica matching.