Phase-Locked Loop (PLL) With High-Pass Filter and Adaptive Control for Sub-Synchronous Oscillation (SSO) Mitigation in Weak Grids With Inverter-Based Resources

Abstract

The increasing penetration of inverter-based resources (IBRs) has reduced system inertia and increased the susceptibility of weak grids to sub-synchronous oscillations (SSOs). Under low short-circuit ratio (SCR) conditions, grid-following converters may interact adversely with grid impedance; phase-locked loop (PLL) dynamics may amplify low-frequency oscillations. This paper proposes an enhanced PLL structure that integrates a high-pass filter (HPF) and an adaptive gain mechanism to mitigate SSOs in grid-following inverters operating under weak-grid conditions. The HPF attenuates low-frequency disturbance components within the synchronization loop, while the adaptive mechanism dynamically adjusts PLL sensitivity according to operating conditions. A dq-frame small-signal model of an LCL-filtered inverter is developed, and a closed-form positive-sequence output impedance model is derived to characterize the influence of the proposed PLL on sub-synchronous dynamics. The analysis demonstrates that the proposed structure reshapes the inverter impedance characteristics within the 10-60 Hz range and improves damping behavior under decreasing SCR conditions. MATLAB/Simulink simulations under representative weak-grid scenarios validate the analytical findings and demonstrate effective suppression of SSOs without degrading steady-state synchronization performance. The proposed approach provides a practical synchronization framework with improved damping and impedance-based stability characteristics for inverter-dominated weak grids.