PIMID is an execution- and trace-driven full-system simulator that closes gaps in the PIM design space and shows that the memory technology alone moves execution time by more than an order of magnitude and that the best host main memory is not the best PIM substrate.
Abstract
Processing-in-Memory addresses the memory wall by co-locating computation with memory, but because real PIM hardware remains scarce, simulation is the primary way to explore the PIM design space. Yet existing PIM simulators each cover only part of that space: they typically model a single memory technology, fix processing elements at one level of the memory hierarchy, support a single execution model, and stop at the device boundary. We therefore present PIMID, an execution- and trace-driven full-system simulator that closes these gaps in one tool. PIMID supports both the shared-memory and message-passing execution models, running annotated parallel code in OpenMP and MPI side by side across eleven memory technologies (seven DRAM standards, SRAM, and three non-volatile memories); it places PEs anywhere from subarrays to logic dies, sweeps PE count and core-model fidelity, and prices the in-memory network per technology from measured congestion. Its single-process host-device co-simulation resolves an end-to-end time and energy breakdown (host preparation, device compute, and explicit boundary charges) that device-only tools cannot produce. Across the resulting dual-execution-model dataset, PIMID shows that the memory technology alone moves execution time by more than an order of magnitude and that the best host main memory is not the best PIM substrate; that regular kernels scale superlinearly with PE count as in-memory bandwidth co-scales with compute; that graph traversal under message-passing hits a collective-communication wall absent under shared memory; and that at full-system scope the offload trades time for energy only on the bandwidth-class memory: shared-memory offload saves energy on HBM3 while a 16-core host keeps every end-to-end time win. PIMID's plugin interfaces let new engines and models be added through standardized YAML specifications as PIM technology evolves.
Results show that standardizing the host-interface layer reduces both the engineering cost of PIM simulator development and the energy overhead of simulation-driven workload evaluation, while reducing host CPU utilization and package energy by up to 50% on transfer-intensive workloads.
VIPER is presented, a unified, lightweight, and architecture-aware performance evaluation framework for PIM DSE, providing rapid architecture-aware performance estimates for iterative DSE without repeated cycle-accurate simulation.
Hao-Ran Geng, T. Pereira, Xiaoyang Lu et al.· 0 citations
GUMPIM is proposed, a PIM system that allows interleaved CPU pages and non-interleaved PIM pages to coexist in a Unitary and Malleable memory space with Guaranteed PIM page allocation and enables zero-copy during PIM task offloading and maintains CPU memory bandwidth while ensuring low PIM offloading overhead.
Yilong Zhao, Fang-Xin Liu, Yi-Wei Hu et al.· ACM Transactions on Architec...· 2 citations
Modern systems-on-chip (SoCs) rely on heterogeneous accelerators for performance scaling. Memory access is a critical bottleneck, but the complexity of cache coherence and nuances of weak memory consistency models (which may vary from system to system) represent a significant designer burden to every load/store unit th...
Joseph Maheshe, G. Lemieux· IEEE International Conferenc...· 3 citations
SerMC is proposed, a memory-controller-based tripwire mechanism that validates accesses when metadata arrives from Dynamic Random Access Memory and extends enforcement to DRAM-bound accesses issued by both processors and DMA-capable devices, and provides practical average-case overhead but still exposes a clear worst-c...
Gen Xu, Li Lv, Jiayan Dong· Computers, Materials & C...· 0 citations
A hardware-software co-design framework that unifies distributed compute, memory, and communication into a seamless processing-communication fabric is presented and a prefill-decode disaggregation approach that dynamically reconfigures PE organizations to maximize resource utilization is presented.