Energy‐Efficient Cross‐Layer Communication Using Adaptive Flow Control in 3D Wireless Network‐on‐Chip Architectures
TL;DR
Results demonstrate that CLARET is a scalable, energy‐aware communication model with real‐time adaptability—opening a promising avenue for intelligent, high‐performance NoC architectures.
Abstract
With the exponential growth in core density and workload complexity in modern chips, traditional two‐dimensional (2D) Network‐on‐Chip (NoC) architectures face critical limitations in scalability, thermal management, and energy efficiency. While three‐dimensional (3D) NoCs with wireless interconnects (WiNoC) offer improved vertical bandwidth and spatial integration, existing solutions such as DyAD, RC‐NoC, and CE‐NoC often rely on static routing and isolated flow control strategies that fail under dynamic traffic conditions, leading to congestion, energy inefficiency, and latency bottlenecks. Addressing these gaps, this study proposes CLARET (Cross‐Layer Adaptive Routing and Energy‐efficient Transport), a novel, decentralized communication framework that integrates dynamic flow control, cost‐based adaptive routing, and real‐time feedback across physical, MAC, and network layers. CLARET is implemented using a custom cycle‐accurate Python‐based 3D WiNoC simulator that incorporates both synthetic and trace‐driven traffic models. The framework dynamically adjusts packet injection rates, reroutes flows based on energy, congestion, and thermal metrics, and employs predictive traffic estimation using exponential smoothing. Experimental results show that CLARET reduces latency by up to 20%, lowers energy consumption by 14.4%, and enhances throughput by 23.5%, outperforming state‐of‐the‐art methods under varying traffic scenarios and workloads. The system maintains a packet delivery accuracy of 92%, marking a significant performance gain over existing protocols. These results demonstrate that CLARET is a scalable, energy‐aware communication model with real‐time adaptability—opening a promising avenue for intelligent, high‐performance NoC architectures. The proposed framework, with its unique cross‐layer synchronization and predictive control, offers a transformative step forward for next‐generation multicore design.