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CAPS: Controlled Adaptive Partitioning of STLB

Aug 2026 · International Symposium on VLSI Design and Test · pp. 519-524 · 0 citations · 7 references

Abstract

Address translation is a critical component of modern processors. The second-level TLB (STLB) plays a key role in reducing translation latency. However, it is shared between instruction and data translations, leading to contention. This sharing introduces destructive interference, which increases misses and degrades performance. In this work, we show that STLB interference is both significant a nd n on-uniform. W e observe up to 46% cross-interference between instruction and data translations. We further show that this behavior varies across sets, making uniform management ineffective. To address this, we propose CAPS, an adaptive STLB partitioning mechanism. CAPS dynamically allocates ways between instruction and data translations based on runtime utility. More importantly, CAPS operates at the set level, enabling fine-grained c ontrol over resource allocation. We implement CAPS in a cycle-accurate simulator and evaluate it across diverse workloads. Static partitioning provides negligible gains, while global dynamic schemes improve performance by only 0.6%. In contrast, CAPS achieves up to 3% IPC improvement with a mean of 1.1% and consistently reduces STLB misses. Our results highlight a key insight: adaptation alone is not sufficient; granularity is critical. By enabling set-aware decisions, CAPS effectively mitigates interference and improves translation efficiency.

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