Intelligent Circuit Design: Exploring Artificial Intelligence for Logic Gate Synthesis and Optimization

Abstract

Modern integrated circuits contain billions of logic gates, while thermal and sub-micron parasitic limits make every design decision more expensive. Classical logic synthesis relies on deterministic minimization and hand-engineered heuristics that struggle to balance Power, Performance, and Area (PPA) at the same time. This paper reviews how Artificial Intelligence (AI) can support logic gate synthesis in Electronic Design Automation (EDA): Graph Neural Networks (GNNs) for circuit representation and early PPA prediction, Reinforcement Learning (RL) for restructuring And-Inverter Graphs (AIGs) and Majority-Inverter Graphs (MIGs), and Transformer-based Large Circuit Models (LCMs) and Large Language Models (LLMs) for hardware generation. Building on the survey of Astillero (2026), it proposes a verification-first hybrid framework in which learned models suggest optimizations and formal equivalence checking guarantees correctness, together with an experimental protocol for evaluating it against classical flows.