Design of a Flexible Hardware Accelerator for Fast Convolutions Using Row-Stationary Dataflow

Abstract

The growth of Convolutional Neural Networks (CNNs) in applications such as image classification and real-time object detection is limited by high computational and energy costs, especially for resource-constrained embedded systems. To address this challenge, this paper presents a fully open-source and flexible hardware accelerator based on the Row-Stationary dataflow. The design supports a wide range of input feature map dimensions, filter sizes, and strided convolution operations. Synthesized in 65 nm CMOS at 200 MHz and evaluated with LeNet-5, the accelerator achieves up to $180\times$ speedup and $12.77\times$ energy reduction compared to a RISC-V CPU. Compared to prior fixedshape designs, the proposal delivers $2.35 \times$ higher performance and $1.56 \times$ better energy efficiency, offering a compact, adaptable solution for high-performance and low-power embedded AI.