Impact of Channel Scaling on IGZO TFT-Based 6T1C Synaptic Cells for Analog Neuromorphic Operation

Abstract

Indium–gallium–zinc oxide (IGZO) thin-film transistor (TFT)-based 6T1C synaptic cells are promising for capacitor-based analog neuromorphic synapses, yet the impact of channel scaling on retention and weight-update characteristics remains insufficiently understood. In this work, calibrated technology computer-aided design simulations of back-gate staggered IGZO TFTs clarify how channel length and thickness scaling jointly affect the retention behavior of IGZO 6T1C cells and the required storage capacitance. When the IGZO TFT is embedded in a 6T1C cell, retention is governed by both steady-state source–drain leakage and displacement currents associated with the dynamics of the floating node, leading to an optimal channel-length window that maximizes the <italic>RC</italic> time constant (on the order of <inline-formula> <tex-math notation="LaTeX">${10}^{{4}}$ </tex-math></inline-formula> h). Based on this analysis, we define a retention-equivalent capacitance, <inline-formula> <tex-math notation="LaTeX">${C}_{\text {req}}$ </tex-math></inline-formula>, and co-optimize the channel dimensions and the storage capacitor, reducing <inline-formula> <tex-math notation="LaTeX">${C}_{\text {req}}$ </tex-math></inline-formula> by over two orders of magnitude, down to sub-pF values without sacrificing the target <italic>RC</italic> constant. Circuit-level simulations confirm that with suitable bias and pulse conditions, the scaled cells maintain linear and symmetric multilevel weight updates, indicating the potential for reduced-footprint IGZO synaptic arrays.