Hardware Implementation of HXTS Dedicated Algorithm Based on Sector Encryption

Abstract

With the acceleration of global digitalization, the demand for storage security has been continuously rising. Existing hardware encryption products are plagued by poor scenario adaptability, unbalanced hardware resource overhead and limited functional coverage, which cannot satisfy the service requirements of high-end storage systems. As a novel tweakable block cipher specialized for sector encryption, the HXTS algorithm boasts high security strength and flexible scene compatibility, possessing prominent value for hardware engineering deployment. This paper concentrates on the hardware-oriented implementation of HXTS and develops a fully modular hardware architecture for the algorithm. Multiple layered optimization schemes are adopted, including offline precomputation of high-order key powers, time-division multiplexing of finite-field computing units, timing delay synchronization, and partition multiplexing storage for multi-algorithm keys, which achieves an optimal balance between hardware area and performance. A multi-layer test platform integrating VCS functional simulation, FPGA prototype verification and standardized UVM validation is constructed. Horizontal comparisons with XTS and HCTR are performed under identical experimental constraints, and quantitative experimental evaluations are conducted from dimensions of hardware area, timing performance and power consumption. The measured experimental results reveal that the designed hardware IP realizes complete timing closure with zero timing violations and delivers a peak throughput of 7.57 Gbps. The overall performance of HXTS is slightly inferior to XTS but superior to HCTR, which can satisfy the engineering deployment requirements of high-end embedded storage encryption.