A Reconfigurable Multi-Algorithm Cryptographic IP Core Based on Operator Sharing

Abstract

Multi-protocol security platforms often integrate block, stream, and ARX ciphers on the same reconfigurable hardware. Instantiating independently optimized cipher cores preserves algorithm structure but duplicates linear bitwise logic and routing resources. This paper presents a reconfigurable multi-algorithm cryptographic IP core for AES, SM4, ZUC, and ChaCha based on operator-level sharing. The design keeps nonlinear and state-update logic inside each cipher core, while recurring XOR aggregation, shift, and rotation operations are implemented through a shared stateless operator layer under a unified top-level controller. Evaluation with the Verilog-to-Routing flow shows that, compared with an unshared baseline using the same integration framework, the proposed implementation reduces Configurable Logic Block utilization by 23.1% and total routing wirelength by 17.7%, with a 3.5% reduction in maximum operating frequency. The results demonstrate that operator-level sharing can reduce redundant hardware with limited timing impact.