Early-Stage Dynamic Power Estimation for CNN Accelerator Design via Frequency-Scalable Polynomial Regression

Abstract

Energy efficiency is a critical design constraint in FPGA-based embedded systems that deploy convolutional neural networks (CNNs). Rapid and accurate exploration methods facilitate optimized implementations. This paper proposes a frequency-scalable power modeling framework for CNN intel-lectual property (IP) libraries on FPGAs, combining polynomial regression with a separable frequency-scaling formulation. The models estimate dynamic power directly from the data and coefficient bit widths and operating frequency, enabling the rapid evaluation of new configurations during design space exploration. Experimental validation on Zynq UltraScale+ and Spartan-7 devices across convolution, activation, and pooling IPs demonstrates $R^{2}$ above 0.97 and MAPE below 4%, confirming high prediction accuracy across operator types. A LeNet-based CNN use case illustrates how the framework enables IP selection and frequency tuning under strict power budgets, supporting power-aware architectural decisions from the earliest stages.