Parameterizing DC Circuit Breaker Interruption Characteristics for Mapping HVDC Cable Transient Stress Regimes

Abstract

The transition from point-to-point HVDC links to multiterminal HVDC (MT-HVDC) grids increases the need to understand how the interruption of DC current shapes transient dielectric stress on connected cable systems. This paper develops a compact parameterization of the DC circuit breaker–cable interface in a reduced 525 kV MT-HVDC grid. The interruption process is characterized by transient interruption voltage (TIV), fault neutralization time, fault current limiting reactor (FCLR) value, and source-side condition. Kirchhoff-based circuit relations interpret the dominant mechanisms, while EMT simulations with a frequency-dependent cable model quantify the healthy-cable voltage response. A 54-case screening study shows that the highest peak stress occurs for high TIV, long tf, low FCLR, and source-supported operation. Several cases exceed the DC long transient overvoltage (DC-LTrOV) reference level, showing that TIV reduction or source removal alone is insufficient to mitigate the associated cable stresses. The results provide traceable input for insulation coordination and assessment of interruption-driven cable stress exposure.