Towards AI-Assisted Hardware Engineering: An Overview of LLM-Driven RTL Design Frameworks

Abstract

Large Language Models (LLMs) are increasingly being explored for register-transfer-level (RTL) generation, hardware verification, debugging, and design automation tasks. Unlike traditional electronic design automation (EDA) workflows that rely heavily on formal methods and handcrafted heuristics, LLM-based systems introduce natural-language-driven hardware synthesis and reasoning capabilities. Recent work has illustrated promising results in Verilog generation, testbench synthesis, simulation-guided refinement, and retrieval-augmented hardware design. However, existing approaches remain fragmented across different architectures, benchmarks, and evaluation methodologies, while challenges such as functional correctness, silent failures, scalability, and hardware-aware reasoning remain unresolved. This paper presents a focused overview of LLM-assisted RTL generation and verification systems. We organize existing methods into direct generation, retrieval-augmented, verification-aware, and agentic multi-stage architectures, and discuss commonly used benchmarks, evaluation metrics, and tool flows. Finally, we highlight major limitations and outline future research directions toward reliable and production-ready AI-assisted hardware design systems.