Hardware Acceleration Techniques for Blockchain Cryptography: ECC and Post-Quantum Approaches–A Systematic Review

Abstract

Modern blockchain systems impose distinct cryptographic requirements, including pairing-based signatures for Ethereum, multi-scalar multiplication (MSM) for zero-knowledge proofs (ZKPs), and post-quantum migration, which existing hardware implementations largely overlook. In this paper, we present a PRISMA 2020-compliant systematic review that analyzes Field-Programmable Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) implementations of Elliptic Curve Cryptography (ECC) and Post-Quantum Cryptography (PQC) from 2018 to 2025. We evaluate these across four blockchain node categories: full nodes, light clients, ZKP provers, and validators. From 688 initial records, rigorous screening yielded 56 FPGA implementations, 16 ASIC designs, and 3 hybrid architectures. Our findings reveal critical gaps between academic research and deployment reality: there is minimal hardware support for the pairing-friendly curves essential for Layer-2 scaling and zkRollups, as well as a lack of hybrid architectures preparing for the imminent post-quantum transition. Performance analysis shows that FPGAs achieve moderate throughput with high energy efficiency (hundreds to thousands of operations per joule), while ASICs reach significantly higher performance at substantially greater costs. PQC schemes consistently exhibit notable area overhead and memory consumption. Crucially, side-channel security remains underaddressed, with no implementations achieving both high performance and validated resistance. To bridge these gaps, we extract four security-aware design patterns, establish a platform selection framework integrating throughput-cost-security trade-offs, and identify five research priorities: standardized benchmarking, hybrid architectures, validated security-performance co-design, energy-proportional implementations, and protocol-hardware co-optimization.