ASIC Implementation of a Support Vector Machine with Emphasis on the Multiply and Accumulate Unit

Abstract

Machine learning (ML) algorithms have become a key part of automation. Specialized algorithms have been developed for quality assessment, prediction, and fault detection in various applications, namely, an Heating Ventilation and Air Conditioning (HVAC) system as an industrial application. Related works suggest that these algorithms are primarily implemented on software or Field Programmable Gate Array (FPGA) platforms. In this proposed design, we aim to implement the Support Vector Machine (SVM) on a hardware platform using Hardware Description Language (HDL). This system is designed to receive precomputed features from a Smart Sensor Unit (SSU) over an Inter-Integrated Circuit (IIC) bus and process the same to produce an inference in the form of a 5-class classified result. A minimal approach has been taken to design the custom HDL-based processing architectures and build the system to implement the same in hardware. We have achieved a low latency of 0.798 ms, with low power and area utilization.