Device–Circuit–System Co-Design of Reconfigurable Oxide–Semiconductor 2T Nonvolatile Gain-Cell Memory and Sandwich-3-D LLM Accelerator

Abstract

In this work, we present an oxide–semiconductor (OS)-based 2T nonvolatile gain-cell (NVGC) memory and a “sandwich 3-D” stacking scheme, co-designed using atomic layer deposition (ALD) InOx oxide–semiconductor FETs (OSFETs) and OS-ferroelectric FETs (FeFETs), for efficient large language model (LLM) acceleration. The new 2T-NVGC enables native, in-memory reconfiguration of static/dynamic kernels for transformers and context-switching workloads, while realizing efficient floating point (FP)/integer (INT) compute-in-memory (CIM). With full-stack, cross-layer co-designs, we present the first complete mixed-signal physical design implementation of an OS-on-CMOS 3D-integrated circuit (IC) with 32.9 TOPS/W energy efficiency and 102.4 TOPS/mm2 compute density. The post-3D-layout simulations calibrated with device experiments demonstrate that the 3D-NVGC LLM accelerator delivers a <inline-formula> <tex-math notation="LaTeX">$52.3\times $ </tex-math></inline-formula> gain in holistic system efficiency over planar CMOS-based and a <inline-formula> <tex-math notation="LaTeX">$3.2\times $ </tex-math></inline-formula> gain over 3-D dynamic random-access memory (DRAM)-based solutions, respectively.