An Energy-Efficient 10T2R NVSRAM Bitcell Using Decoupled Bilateral RRAM Paths

Abstract

This paper presents a novel 10T2R resistive random-access memory (RRAM) based nonvolatile SRAM (NVSRAM) bitcell for energy-efficient and reliable nonvolatile operation. The proposed architecture employs decoupled bilateral RRAM paths to eliminate the DC short-circuit issue present in conventional NVSRAM designs, thereby improving restore reliability, stability, and robustness. The NVSRAM bitcell is implemented using TSMC 65 nm CMOS technology, while the RRAM device is adopted from the Stanford Verilog-A compact model calibrated with $\mathbf{H f O}_{x}$-based RRAM characteristics. Simulation results demonstrate femtojoule-range store and restore energy consumption, achieving a 14.41% reduction in store energy and a 31.16% reduction in restore energy compared with existing NVSRAM bitcell. In addition, Monte Carlo and process variation analyses confirm stable and reliable operation under variability conditions. The proposed design is therefore well suited for low-power embedded systems, edge AI, IoT, and instant-on computing applications.