MECA-CiM: A Shared-MicroExponent-aware Configurable Analog Compute-in-Memory Macro for Efficient Inference

Abstract

SRAM-based compute-in-memory (CiM) accelerators have emerged as a promising approach for low-power inference in edge devices by alleviating data-movement overhead. However, existing CiM designs face a fundamental trade-off: integer-based CiM suffers from limited numerical accuracy, while floating-point CiM incurs substantial energy and area overhead due to complex exponent handling and peripheral circuits. This paper presents an analog CiM accelerator based on the SMX6 format, which extends the block floating-point (BFP) representation with a lightweight microexponent (μE) shared by pairs of values. By embedding μE-aware scaling directly into the analog MAC operation, the proposed design achieves improved numerical fidelity without introducing costly digital shift-and-align logic. To further address accuracy degradation caused by analog dynamic-range limitations, the accelerator supports configurable block granularity, allowing the accumulation range to be adaptively adjusted to match layer-wise activation distributions and ADC input constraints. Implemented in 28nm CMOS technology, the proposed SRAM-based ACiM achieves accuracy close to the FP32 baseline across diverse workloads, while delivering up to 54.19 TOPS/W energy efficiency and 4.66 TOPS/mm2 area efficiency. These results demonstrate that micro-exponent-aware analog CiM with configurable granularity is an effective and practical design point for energy-efficient edge inference.