A High-Efficiency, High-Accuracy Approximate Multiplier for DNN Accelerators

Abstract

Multipliers dominate the critical path, power consumption, and silicon area of deep neural network (DNN) accelerators. This paper presents a high-efficiency 7-bit unsigned approximate multiplier tailored for DNN accelerators. Unlike conventional signed 8-bit designs—where the sign bit is handled separately via XOR—the proposed architecture directly adopts a 7-bit unsigned format. Based on distribution-aware approximation, the partial-product reduction stage is redesigned with exact compressor allocation, while a lightweight bit-flipping technique increases bit-level sparsity, reducing dominant partial products by over 50% with only small compensable errors. FPGA implementation shows strong hardware efficiency, achieving up to 28.7% reduction in logic resources and 13.4% lower dynamic power compared with recent high-accuracy approximate multipliers. DNN inference evaluation on representative models and datasets shows minimal accuracy degradation by 0.27% on LeNet–MNIST and competitive performance on more challenging tasks, outperforming PAM1 and PAM2 by $\mathbf{4 . 4 8} \boldsymbol{\%} \boldsymbol{-} \mathbf{4 . 7 5 \%}$ on LeNet–SVHN. These results demonstrate an effective balance between hardware efficiency and inference accuracy for energy-efficient DNN accelerators.