Microprocessor Programming: From Architecture to Bare-Metal Firmware Design

Abstract

This laboratory manual, Microprocessor Programming, provides a hands-on, hardware-aware curriculum designed to bridge abstract computer organization concepts with practical bare-metal firmware design. By guiding students from low-level CISC assembly languages through RISC embedded platforms to high-level abstraction frameworks (Arduino C++), the manual provides a structured pathway for developing hardware-software co-design proficiency. This laboratory manual is aligned with the academic and competency requirements set by the Commission on Higher Education (CHED) for Philippine Higher Education Institutions (HEIs) offering undergraduate degrees in engineering: BS Electronics Engineering (BSECE): Compliant with CHED Memorandum Order (CMO) No. 101, Series of 2017 (Policies, Standards and Guidelines for the Bachelor of Science in Electronics Engineering Program), specifically covering the core technical requirements for Microprocessor & Microcontroller Systems and Embedded Systems. BS Computer Engineering (BSCpE): Compliant with CHED Memorandum Order (CMO) No. 87, Series of 2017 (Policies, Standards and Guidelines for the Bachelor of Science in Computer Engineering Program), supporting professional courses in Microprocessor Systems, Computer Architecture and Organization, and Embedded Systems Design. Pedagogical Progression & Technical Scope The manual establishes an architectural progression across eight laboratory modules, transitioning from 16-bit microprocessor software simulation to bare-metal microcontroller unit (MCU) peripheral control: [Phase 1: MPU Architecture & Assembly] ➔ [Phase 2: MPU vs. MCU Transition] ➔ [Phase 3: RISC & Interrupt Systems] ➔ [Phase 4: Hardware Abstraction & Trade-offs] (Labs 0 - 4: 8086 CISC) (Lab 5: 8085 vs. 8051) (Labs 6 - 7: PIC16F84A) (Lab 8 / HLA 1-2: ATmega328P) 1. Fundamental Architecture & Instruction Set Abstraction (Labs 0–4) x86 Architecture & Assembly Fundamentals: Uses the Intel 8086 CPU to map C++ high-level structures (loops, branches, dynamic memory) directly to registers, instruction pointers, and status flags (ZF, CF, SF). I/O Paradigms & Virtual Interfacing: Differentiates Isolated Port-Mapped I/O (IN/OUT) from Memory-Mapped I/O. Students examine DOS/BIOS system calls (INT 21h, INT 14h), construct custom Interrupt Service Routines (ISRs) in the Interrupt Vector Table (IVT), and program closed-loop peripheral hardware controllers (Virtual Parallel Printer, Virtual LEDs, Serial Chat, MicroMouse Robotics). 2. Architectural Evolution: MPU to Integrated MCU (Lab 5) Von Neumann vs. Modified Harvard Architecture: Traces the structural split between general-purpose microprocessors (Intel 8085 Princeton model with multiplexed address/data buses) and dedicated microcontrollers (Intel 8051 Harvard model with separate program/data memory spaces). Mixed-Signal & Peripheral Control: Demonstrates single-bit addressable Special Function Registers (SFRs), hardware UART baud-rate generation, ADC0804 sampling, and R-2R DAC output scaling. 3. RISC Microcontroller Mechanics & Hardware Interrupts (Labs 6–7) CISC to RISC Paradigm Shift: Explores the Microchip PIC16F84A Harvard RISC architecture (35 core instructions, 4-clock instruction cycle TCY=4fOSC) and the Working Register (W) execution bottleneck. Real-Time Peripheral Control: Focuses on tri-state direction registers (TRISA/TRISB), persistence-of-vision (POV) display multiplexing, software switch debouncing, and 3D nested delay loop math. Non-Blocking Concurrency: Integrates multi-interrupt handling at a single hardware vector (0x0004), utilizing non-destructive register swapping (SWAPF) for W/STATUS context preservation, Timer0 prescaler scaling, and falling-edge hardware interrupt inputs (RB0/INT). 4. Direct Register Access vs. High-Level Abstraction (Lab 8 & HLA Modules) Bare-Metal AVR Programming: Interfacing with the Microchip ATmega328P using Direct Register Access (DDRx, PORTx, PINx). Execution Efficiency & Safety: Compares clock cycle latency and memory footprints across raw Assembly (CBI/SBI - 2 cycles), Direct Register C (2 cycles), and Arduino Hardware Abstraction Layer functions (digitalWrite() - 40+ cycles). Safety-Critical Bitwise Operations: Emphasizes bitwise mask manipulation (&= ~ vs. |= ~) to prevent catastrophic register overwrites in real-time embedded systems.