Inspection Factorization for Hardware-Efficient 2D Fast Convolution

Abstract

Fast convolution is widely used to reduce the arithmetic cost of small-kernel CNN convolutions. However, its hardware efficiency depends not only on the number of transform-domain multiplications, but also on the complexity of the transform stages. This work proposes Inspection Factorization (IF) as an alternative to conventional Winograd and Toom-Cook schemes for $3 \times 3$ convolution under a unified RTL architecture. IF is compared to a straightforward MAC-based baseline, referred to as Naïve, under identical workload and clock constraints at two operating points: balanced, corresponding to the best area-performance trade-off, and maxMAC, corresponding to the maximum number of MAC units used by the IF in this work. Relative to Naïve, IF achieves a performance gain of 69% to 83% for both operating points. The corresponding area variation ranges from a 2% reduction to a 38% increase, while power consumption increases by 44% to 88%. Despite this power penalty, IF reduces energy consumption by 57% to 69%. Compared with other fast-convolution alternatives, IF offers an intermediate trade-off between performance and implementation cost, with lower transform overhead than larger Toom-Cook configurations and higher performance than smaller Winogradbased alternatives.