Using Hardware-Emulated Fault Injection on the Evaluation of a Mixed-Signal Test Pattern Generation Tool

Abstract

This paper presents a Hardware-Emulated Fault Injection framework for evaluating a previously proposed test pattern generation tool for mixed-signal circuits. Operating directly on the SPICE netlist of the circuit under test (CUT), the computational tool conducts successive fault simulations to evaluate the DC, AC, and transient behaviors across internal nodes and external outputs. It then produces a test sequence that identifies optimal stimuli and observation points to maximize fault coverage. For experimental validation, a simple operational amplifier and a StrongARM comparator were implemented using MOS transistors of a commercial device. The SPICE netlist and corresponding transistor models were provided as inputs to the tool. The generated test sequence was then applied to both physical circuits with open and short faults injected into the hardware, considering the same previously simulated fault model. Experimental results show good fault coverage and good agreement with the simulations. By considering as case studies a pure analog linear circuit and a non-linear, clocked, mixed-signal (MS) block, the feasibility of applying the tool to different kinds of MS devices is demonstrated.