Statistical and Hardware Validation of Arbiter PUF for Secure and Energy Efficient IoT Devices

Abstract

The rapid growth of the Internet of Things (IoT) has led to billions of interconnected devices across critical domains such as healthcare, transportation, and smart systems, introducing major challenges in security, privacy, interoperability, and resource management. These issues are amplified by large-scale deployment and the limited computational and energy capabilities of edge devices, making them vulnerable to various attacks. Existing solutions include blockchain, fog computing, machine learning, and edge-based approaches. This work focuses on lightweight hardware security using Arbiter Physical Unclonable Functions, which leverage intrinsic process variations to generate unique device responses. This work focuses on lightweight hardware security using a 15-bit challenge Arbiter Physical Unclonable Function (PUF) implemented on an Altera Cyclone IVE FPGA. Challenge Response Pair (CRP) data is experimentally extracted using a logic analyzer for accurate hardware-level evaluation. The design achieves near-ideal uniqueness of about 48 to 49.6 percent, uniformity of 49 to 51 percent, and reliability between 95 and 99 percent. Analysis of nearly one million CRPs shows low bias with high entropy and zero bit error rate, while NIST STS results confirm strong randomness at a 0.01 significance level. A core dynamic power consumption of only 5.20 mW confirms the lightweight nature of the proposed APUF architecture, making it well suited for low power hardware security applications.