Hardware-Efficient 5 × 5 S-Boxes With Strong Cryptographic Criteria for Lightweight Cryptography

Abstract

Substitution boxes (S-Boxes) are essential nonlinear components in cryptography. This work presents a randomized, coordinate-function-first framework for constructing and selecting <inline-formula> <tex-math notation="LaTeX">$5\times 5$ </tex-math></inline-formula> S-Boxes. Balance is imposed by construction at the Boolean-function level; retained coordinate functions satisfy nonlinearity <inline-formula> <tex-math notation="LaTeX">$NL(f)=12$ </tex-math></inline-formula> and the exact strict avalanche criterion (SAC), and fixed-order 5-function combinations are subsequently evaluated as complete vectorial mappings. The selected permutation achieves nonlinearity <inline-formula> <tex-math notation="LaTeX">$NL(S)=12$ </tex-math></inline-formula>, differential probability (DP) = 0.0625, maximum absolute linear bias <inline-formula> <tex-math notation="LaTeX">$LB_{\max }=0.125$ </tex-math></inline-formula>, exact entry-wise SAC = 0.5, exact directional bit independence criterion based on SAC (BIC-SAC) = 0.5, bit independence criterion nonlinearity (BIC-NL) = 12, and no fixed or opposite fixed points. The selected S-Box has a direct algebraic normal form (ANF) realization with 10 AND gates and 27 XOR gates. In addition, an XOR-oriented factorized realization reduces the XOR count to 13 at the cost of 15 AND gates and 6 NOT gates. A shared-affine realization is also introduced to expose additional logic-sharing opportunities to technology mapping. For hardware evaluation, the selected S-Box is implemented using both direct truth-table register-transfer-level (RTL) descriptions and mapping-specific optimized Boolean realizations under a common Cadence Genus 23.14/Nangate45 45-nm synthesis flow. The factorized implementation achieves an area of <inline-formula> <tex-math notation="LaTeX">$34.314~\mu \mathrm {m}^{2}$ </tex-math></inline-formula>, a critical-path delay of 0.251 ns, and an area-delay product (ADP) of <inline-formula> <tex-math notation="LaTeX">$8.613~\mu \mathrm {m}^{2}\!\cdot \!\mathrm {ns}$ </tex-math></inline-formula>. The shared-affine realization further reduces the mapped area to <inline-formula> <tex-math notation="LaTeX">$32.718~\mu \mathrm {m}^{2}$ </tex-math></inline-formula> and the preliminary total power to <inline-formula> <tex-math notation="LaTeX">$4.231~\mu \mathrm {W}$ </tex-math></inline-formula>. Under the reported flow, the factorized network provides the minimum delay and ADP, whereas the shared-affine network provides the minimum mapped area and preliminary power among the evaluated realizations of the selected mapping.