Joint Multiplier–Adder Approximation with Flag-Based Error Recovery for BF16 Digital Compute-in-Memory
TL;DR
The Proposed scheme achieved the lowest BF16-referenced Layer NRMSE and Logit NRMSE among the evaluated Baseline, DIMC-S-derived, LSAC OR+SXAFA-derived, and Proposed schemes, while the Top-1 accuracy difference relative to the Baseline remained within −0.02%p to +0.12%p.
Abstract
Digital computing-in-memory (DCIM) provides deterministic floating-point computation but incurs substantial area and power overhead from replicated mantissa multipliers and adder trees. This work proposes an error-recoverable BF16 DCIM arithmetic unit that jointly approximates a 2-bit multiplier and the first adder stage. For the 11 × 11 input, the multiplier outputs 0111 instead of the Baseline 1111, converting the error from +6 to −2 and fixing the product MSB to 0. This enables the first adder stage to be reduced from 4 bits to 3 bits. A lightweight flag detects the same error condition and is reused as a carry input for local compensation, avoiding a separate multi-bit correction circuit. Hierarchical design-space exploration selected the 0111 approximation with carry compensation at bit position 1. Transistor-level evaluation showed reductions of 14.81% in transistor count and 28.56% in average power relative to the Baseline. Across ResNet18, VGG16-BN, and AlexNet on CIFAR-10 and CIFAR-100, the Proposed scheme achieved the lowest BF16-referenced Layer NRMSE and Logit NRMSE among the evaluated Baseline, DIMC-S-derived, LSAC OR+SXAFA-derived, and Proposed schemes, while the Top-1 accuracy difference relative to the Baseline remained within −0.02%p to +0.12%p. These results demonstrate an improved hardware–accuracy trade-off without retraining or data rearrangement.