APM-CIM: An Array Partition Multi-Macro CIM System With Dynamic Sparse Approximation for Neural Network Edge Applications

ReHGNN: A Digital-Analog Processing-in-Memory Architecture for Sparse-Dense Matrix Multiplication in Hypergraph Neural Networks

ReHGNN is presented, the first hybrid digital/analog PIM architecture for HGNN inference, and a greedy heuristic algorithm is proposed to further improve the utilization of ReRAM resource.

UvA-DARE (Digital Academic Repository) PELSI: Power-Efficient Layer-Switched Inference

Hybrid RRAM-SRAM Computing-in-Memory Architecture Enabling Inference and Fine-Tuning

The hybrid RRAM-SRAM CIM architecture that enables inference and finetuning is proposed and achieves the higher peak energy efficiency of 20.76 TOPS/W, outperforming the state-of-the-art by 2.30×.

Unifying Feed-Forward and Weight-Gradient: An Energy-Efficient Architecture for On-Chip SNN Learning

Spiking neural networks (SNNs) enable efficient on-chip learning but face a critical hardware challenge due to the computational asymmetry between small-kernel convolution operations in the feed-forward (FF) stage and large-kernel ones in the weight-gradient (WG) stage. Directly mapping these conflicting patterns onto...

Energy and Area Efficient Systolic Accelerator for Sparse Neural Networks

A hardware-algorithm co-design approach in which a semi-structured pruning method and a sparsity-aware systolic accelerator are developed jointly and motivated by each other, thereby reducing unnecessary computation and energy consumption.

Optimizing Deep Neural Network Sparse Kernels on Multi-core CPUs

TurboSparse eliminates im2col by executing SpConv directly over a DNN-oriented sparse format to reduce data movement and improve reuse, introduces row-merging micro-kernels guided by an analytical SIMD-utilization model to increase vector-lane occupancy, and fuses consecutive sparse kernels when their combined working...