Aug 2026· IEEE International Conference on Embedded and Real-Time Computing Systems and Applications· pp. 201-208· 0 citations· 22 references
Abstract
Industrial edge platforms increasingly consolidate real-time control and general-purpose workloads on a single system-on-chip (SoC) to reduce costs, power, and complexity. Conventional real-time virtual machine (RTVM) setups, however, typically rely on PREEMPT_RT Linux and commonly reserve at least two CPU cores to isolate real-time tasks from housekeeping, which hinders scalability on resource-constrained edge platforms. This paper investigates whether low-latency Ethernet networking with tight observed tail latency can be sustained in a single-core RTVM configuration. We implement a single-core Zephyr-based RTVM on ACRN and compare it with a single-core PREEMPT_RT Linux RTVM under the same VM topology, using the same directly assigned Intel i226-LM PCIe Ethernet NIC via passthrough and an identical UDP echo workload. Latency measurements across 30 million packets at a traffic rate of 8 thousand packets per second (8 kpps) characterize both averagecase and extreme-tail behavior. PREEMPT_RT Linux shows severe tail amplification even without interference (99.999th percentile: $\mathbf{2 1 6 3} \boldsymbol{\mu} \mathbf{s}$; max: $\mathbf{6 8 7 2} \boldsymbol{\mu} \mathbf{s})$, while Zephyr maintains a tightly concentrated latency distribution (99.999th percentile: $79 \mu \mathrm{s}$; max: $82 \mu \mathrm{s})$. Under full-system noisy-neighbor load, Zephyr preserves sub- $\mathbf{1 0 0}-\boldsymbol{\mu} \mathbf{s}$ observed tail latency, whereas Linux degrades further. These empirical findings provide evidence that a specialized RTOS-based RTVM can sustain tight tail-latency performance and low delay variation on a single core, challenging the conventional two-core provisioning strategy for real-time edge systems.
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KV-cache offload is widely used to stretch GPU memory for LLM serving, but its storage behavior has not been characterized at the block-device level. In this paper, we study LMCache through realworld multi-session workloads that span same/different context $\times$ same/different prompt, using over 100 stateless reques...
Ying He, Dingsen Shi, Yanbo Dai et al.· 2026 International Conferenc...· 0 citations
A standards-based, multi-tenant cloud inference framework that integrates OpenStack orchestration with Single Root I/O Virtualization (SR-IOV)-enabled graphics processing unit (GPU) partitioning to achieve predictable and isolated real-time inference execution.
Rui Ma, Bing-Feng Shi, Xing-Run Ma et al.· Journal of ICT Standardizati...· 0 citations
PANEM is presented, a lightweight event-driven heuristic model that has guided four generations of commercial server-core development at Ampere Computing and shows that a calibrated, contention-aware abstraction can deliver practical predictive value for industrial design-space exploration at simulation costs similar t...
The architecture introduces two reusable system-level design principles: interrupt-independent notification via sequence counters, avoiding OS-mediated jitter as much as possible, and cache-aware core selection based on the non-uniform cache architecture (NUCA) to reduce the variability of access latency, thereby achie...
Hui-Ji Zheng, Qing Liu, Kang Wang et al.· Electronics· 0 citations
A controlled characterization framework that evaluates independently deployed CU and DU functions under matched hardware and traffic conditions and identify distinct CU and DU execution characteristics and motivate function-specific processor analysis and optimization is described.
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