Active $dv/dt$ Control to Minimize Common-Mode Current in SiC Converters

Abstract

Silicon carbide (SiC) MOSFETs, as one of the wideband gap (WBG) switches, are widely adopted in many automotive and industrial applications. The ability to operate at higher switching frequencies with lower switching losses favors SiC over its silicon counterparts. Higher switching frequency reduces the passive filter size, thereby improving the power density of the power converter. Nevertheless, the fast slew rate of SiC MOSFET generates significant common-mode current and EMI noise, violating standards in many applications. In general, switching losses and EMI performance can be balanced using the conventional gate driver (CGD) technique by adjusting the gate resistance. However, several existing solutions on active gate drivers (AGD) show that conventional gate driver (CGD) performance can be further improved with AGDs. This research aims to minimize the parasitic leakage current generated during the switching transition of SiC MOSFETs with a simple addition of intermediate voltages during switching transients. An intermediate gate voltage is introduced during drain-source voltage rise/fall to control the slew rate during transition. The proposed method is simulated using a 10 kW buck converter to investigate its benefits at the power-converter level. The simulation results confirm that the proposed method successfully reduces leakage current without sacrificing the switching loss performance. It is also worth noting that the proposed AGD method also suppresses the common-mode noise peaks in the conducted emissions zone.