Safe Hierarchical Lyapunov Control With a Deterministic Agentic Loop for Autonomous Multi-Cell 6G RAN Slicing

Abstract

Sixth-generation (6G) radio access networks (RANs) must allocate physical resource blocks (PRBs) across network slices with competing service level agreements (SLAs), under a long-term energy budget and a hard per-slot capacity limit. Existing learning-based slicing controllers soften these constraints into penalties or trust regions, and therefore provide only asymptotic, in-expectation guarantees; they converge slowly, offer no per-slot safety while the policy explores, and their action space grows exponentially with the number of slices. This paper presents SHARP (Safe Hierarchical Agentic Resource Planner), a safe hierarchical Lyapunov control architecture with a deterministic agentic loop, whose self-correcting components close a deterministic plan-reason-act-monitor loop: an intent interface decomposes operator intents into slice targets; a planning layer runs entropic online mirror descent over decision frames; a verification layer couples a Lyapunov-driven virtual energy queue with a safety projection onto the capacity set; a worker reserves capacity for ultra-reliable low-latency communication (URLLC) traffic; and a monitor with key performance indicator (KPI) memory corrects the controller online under capacity anomalies and falsified telemetry. Throughout this paper the term “agentic” denotes deterministic closed-loop goal decomposition, planning, verification, action, monitoring, and self-correction executed by fixed rules; the controller contains no language-model component and does not employ open-ended reasoning, tool selection, or inter-agent communication. The analysis establishes a deterministic per-slot capacity guarantee; a throughput-energy tradeoff in which the optimality gap of the implemented algorithm is <inline-formula> <tex-math notation="LaTeX">$B_{0}/V+c_{1}$ </tex-math></inline-formula>, comprising an <inline-formula> <tex-math notation="LaTeX">$\mathcal {O}(1/V)$ </tex-math></inline-formula> decaying term and a fixed, state-independent design offset <inline-formula> <tex-math notation="LaTeX">$c_{1}$ </tex-math></inline-formula> that quantifies the cost of the structural URLLC reservation and conservative throttling, together with <inline-formula> <tex-math notation="LaTeX">$\mathcal {O}(V)$ </tex-math></inline-formula> virtual-queue growth. The offset is derived in closed form and certified against an exact per-slot oracle, at which the measured per-slot gap is <inline-formula> <tex-math notation="LaTeX">$C/V\approx 5.8\times 10^{2}$ </tex-math></inline-formula> bits per slot per cell, or 39.8% of the oracle objective, a fixed price of the structural reservation and the conservative throttle. The analysis also establishes an <inline-formula> <tex-math notation="LaTeX">$\mathcal {O}(\sqrt {T/H})$ </tex-math></inline-formula> manager regret, an exponential-to-polynomial complexity reduction, and vanishing expected power overshoot during learning. In a simulation study over eighteen alternatives, all of them implemented in this study as rule-based or linear-function-approximation representatives of their method families, and twenty seeds, SHARP combines zero URLLC violation with high energy feasibility and achieves the highest energy efficiency among methods that meet the URLLC SLA while requiring no training episodes. An equalized-safety-layer study attributes the nominal safety result precisely: the deterministic reservation, throttle, and projection layer alone reproduces the zero-violation and energy-feasibility figures at nominal stationary load, while the adaptive hierarchy and the monitor provide their primary value under drift, capacity anomalies, and falsified telemetry. Within the same simulation model, its safety behavior is retained through event-driven attack scenarios and carries over without retraining to unseen topologies, offered loads, and networks of one hundred cells. The components map onto the O-RAN architecture, and the profiled per-decision compute time of the controller is 132 to 262 microseconds. All quantitative results are outputs of the stated system-level simulation model of the abstracted traffic, channel, and power dynamics; no hardware or testbed measurements are claimed.