Microsecond-Latency, Fully On-Chip Limit Order Book Prediction on an Edge FPGA: A Lightweight INT8 1D-CNN Hardware–Software Co-Design
Abstract
High-frequency trading demands microsecond, deterministic inference that jitter-prone general-purpose processors cannot deliver, yet fully on-chip edge-FPGA predictors for real-time limit order book (LOB) forecasting remain underexplored. This paper presents a hardware–software co-design that maps a lightweight residual 1D-CNN onto a single standalone edge FPGA for LOB price-movement prediction. On the 144-dimensional FI-2010 dataset with 86,211 parameters, the model achieves a Macro-F1 of 0.8509 on the anchored deployment fold (CF_9). An 8-bit quantization-aware training pipeline with per-channel input weight-folding compresses the model by <inline-formula> <tex-math notation="LaTeX">$3.38\times $ </tex-math></inline-formula> for fully on-chip inference, limiting Macro-F1 degradation to only 1.78 percentage points (to 0.8331), compared with an 11.69-point drop from post-training quantization; a systematic bit-width study identifies INT8 as the Pareto-optimal operating point. Synthesized, placed and routed on a Xilinx Kintex UltraScale KU040, a fully-unrolled latency-optimized architecture reaches a deterministic 57 <inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>s on-chip inference-core latency with zero run-to-run jitter, at a directly measured whole-board power of 3.11 W. On-board execution is bit-exact with the PyTorch INT8 reference across all 31,828 test-day samples, yielding 83.12% accuracy (95% Wilson interval: 82.71–83.53%). For single-sample inference, the standard operating mode for high-frequency trading, it achieves 5.98–<inline-formula> <tex-math notation="LaTeX">$10.44\times $ </tex-math></inline-formula> lower latency and 23.8–<inline-formula> <tex-math notation="LaTeX">$41.6\times $ </tex-math></inline-formula> higher energy efficiency than an NVIDIA RTX 5070 Laptop GPU (measured at 12.39 W), with the range covering both optimized and eager FP32 execution stacks. Verification artifacts, full code and model weights are available at <uri>https://github.com/siyuan-liu-research/LOB-FPGA</uri>